(Singapore)
Product Summary
The EP3C16F484C8N is a lowest power FPGA with security.
Parametrics
EP3C16F484C8N absolute maximum ratings: (1)VCCINT, Supply voltage for internal logic: –0.5 to 1.8 V; (2)VCCIO, Supply voltage for output buffers: –0.5 to 3.9 V; (3)VCCA, Supply voltage (analog) for phase-locked loop (PLL) regulator: –0.5 to 3.75 V; (4)VCCD_PLL, Supply voltage (digital) for PLL: –0.5 to 1.8 V; (5)VI DC, input voltage: –0.5 to 3.95 V; (6)IOUT, DC output current, per pin: –25 to 40 mA; (7)VESDHBM, Electrostatic discharge voltage using the human body model: ±2000 V max; (8)VESDCDM, Electrostatic discharge voltage using the charged device model: ±500 V max; (9)TSTG, Storage temperature: –65 to 150 ℃; (10)TJ, Operating junction temperature: –40 to 125 ℃.
Features
EP3C16F484C8N features: (1)Lowest power consumption due to: TSMC low-power process technology; Altera power-aware design flow; (2)Low-power operation offers the following benefits: Extended battery life for portale and handheld applications; reduced or eliminated cooling system costs; Operation in thermally-challenged environments; (3)Hot-socketing operation support; (4)Configuration security using advanced encryption standard (AES) with 256-bit volatile key; (5)Routing architecture optimized for design separation flow with the QuartusR II software; (6)Design separation flow achieves both physical and functional isolation between design partitions; (7)Ability to disable external JTAG port; (8)Error Detection (ED) Cycle Indicator to core.
Diagrams
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 EP3C16F484C8N |
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IC CYCLONE III FPGA 16K 484FBGA |
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