XC2V1000-5FGG256C

Product Summary

The XC2V1000-5FGG256C is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The XC2V1000-5FGG256C delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15μm / 0.12μm CMOS 8-layer metal process and the XC2V1000-5FGG256C architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the XC2V1000-5FGG256C enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays. As shown in Table 1, XC2V1000-5FGG256C family comprises 12 members, ranging from 40K to 10M system gates.

Parametrics

XC2V1000-5FGG256C absolute maximum ratings:(1)Internal supply voltage relative to GND, VCCINT: –0.5 to 1.65V; (2)Auxiliary supply voltage relative to GND, VCCAUX: –0.5 to 4.0V; (3)Output drivers supply voltage relative to GND, VCCO: –0.5 to 4.0V; (4)Key memory battery backup supply, VBATT: –0.5 to 4.0V; (5)Input reference voltage –0.5 to VCCO, VREF: + 0.5V; (6)Input voltage relative to GND (user and dedicated I/Os), VIN: –0.5 to VCCO + 0.5V; (7)Voltage applied to 3-state output (user and dedicated I/Os), VTS: –0.5 to 4.0V; (8)Storage temperature (ambient), TSTG: –65 to +150℃; (9)Maximum junction temperature, TJ: +125℃.

Features

XC2V1000-5FGG256C features: (1)Industry First Platform FPGA Solution ; (2)IP-Immersion Architecture; (3)Densities from 40K to 8M system gates; (4)420 MHz internal clock speed (Advance Data); (5)840+ Mb/s I/O (Advance Data); (6)SelectRAM Memory Hierarchy; (7)3 Mb of True Dual-Port? RAM in 18-Kbit block ; (8)SelectRAM resources; (9)Up to 1.5 Mb of distributed SelectRAM resources; (10)High-performance interfaces to external memory; (11)DDR-SDRAM interface; (12)FCRAM interface ; (13)QDR-SRAM interface; (14)Sigma RAM interface; (15)Arithmetic Functions; (16)Dedicated 18-bit x 18-bit multiplier blocks; (17)Fast look-ahead carry logic chains; (18)0.15 μm 8-Layer Metal process with 0.12 μm high-speed transistors; (19)1.5 V (VCCINT) core power supply, dedicated 3.3 V ; (20)VCCAUX auxiliary and VCCO I/O power supplies; (21)IEEE 1149.1 compatible boundary-scan logic support; (22)Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in three standard fine pitches (0.80mm, 1.00mm, and 1.27mm); (23)100% factory tested.

Diagrams