(Singapore)
Product Summary
The EP3C55F484C8N is a high functionality, low power and low cost FPGA. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, the EP3C55F484C8N provides the ideal solution for your high-volume, low-power, and cost-sensitive applications.
Parametrics
EP3C55F484C8N absolute maximum ratings: (1)Supply voltage for internal logic: –0.5 to 1.8 V; (2)Supply voltage for output buffers: –0.5 to 3.9 V; (3)Supply (analog) voltage for PLL regulator: –0.5 to 3.75 V; (4)Supply (digital) voltage for PLL: –0.5 to 1.8 V; (5)DC input voltage: –0.5 to 3.95 V; (6)DC output current, per pin: –25 to 40 mA; (7)Electrostatic discharge voltage using the human body model: ±2000 V; (8)Electrostatic discharge voltage using the charged device model: ±500 V; (9)Storage temperature: –65 to 150 ℃.
Features
EP3C55F484C8N fetures: (1)Configuration security using advanced encryption standard (AES) with 256-bit volatile key; (2)Routing architecture optimized for design separation flow with the QuartusR II software: Design separation flow achieves both physical and functional isolation between design partitions; (3)Ability to disable external JTAG port; (4)Error Detection (ED) Cycle Indicator to core: Provides a pass or fail indicator at every ED cycle, Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits.
Diagrams
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 EP3C55F484C8N |
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IC CYCLONE III FPGA 55K 484FBGA |
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EP3C10E144C8N |
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EP3C10E144I7N |
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