EPF10K130EFC484-1N

Product Summary

The EPF10K130EFC484-1N is an Embedded Programmable Logic Device. Based on reconfigurable CMOS SRAM elements, the EPF10K130EFC484-1N architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, the EPF10K130EFC484-1N provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.

Parametrics

EPF10K130EFC484-1N absolute maximum ratings: (1)Supply voltage:–0.5V to 3.6V, –0.5V to 4.6V; (2)DC input voltage:–2.0V to 5.75V; (3)DC output current, per pin: –25mA to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:135℃.

Features

EPF10K130EFC484-1N features: (1)Individual tri-state output enable control for each pin; (2)Open-drain option on each I/O pin; (3)Programmable output slew-rate control to reduce switching noise; (4)Clamp to VCCIO user-selectable on a pin-by-pin basis; (5)Supports hot-socketing; (6)FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays; (7)Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions); (8)Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions); (9)Tri-state emulation that implements internal tri-state buses; (10)Up to six global clock signals and four global clear signals; (11)Fabricated on an advanced process and operate with a 2.5-V internal supply voltage; (12)In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port; (13)ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication; (14)Built-in low-skew clock distribution trees; (15)100% functional testing of all devices; test vectors or scan chains are not required; (16)Pull-up on I/O pins before and during configuration.

Diagrams