EP20K300EQC240-2XN

Product Summary

The EP20K300EQC240-2XN is the first PLD designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the EP20K300EQC240-2XN device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEXTM 20K device. The EP20K300EQC240-2XN is a superset of APEXTM 20K device and include additional features such as advanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. In addition, The EP20K300EQC240-2XN extends the APEX 20K family to 1.5 million gates.

Parametrics

EP20K300EQC240-2XN absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: -0.5 3.6 V; (2)VCCIO: -0.5 to 4.6 V; (3)VI DC input voltage: -2.0 to 5.75 V; (4)IOUT DC output current, per pin: -25 to 25 mA; (5)TSTG Storage temperature No bias: -65 to 150 ℃; (6)TAMB Ambient temperature Under bias: -65 to 135 ℃; (7)TJ Junction temperature: 135 ℃; (8)Ceramic PGA packages, under bias: 150 ℃.

Features

EP20K300EQC240-2XN features: (1)MultiCoreTM architecture integrating look-up table (LUT)logic, product-term logic, and embedded memory; (2)LUT logic used for register-intensive functions; (3)Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM); (4)ESB implementation of product-term logic used for combinatorial-intensive functions.

Diagrams