EPM7256SQC208-7N

PLD, QFP, –2.0 to 7.0V, EPM7256SQC208-7N, –25 to 25 mA

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PartNumber:: EPM7256SQC208-7N

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 07+

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Products Upload time: 2012-06-26

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Part Number:EPM7256SQC208-7N
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Product Summary

The EPM7256SQC208-7N is a high-density, high-performance PLD. Fabricated with advanced CMOS technology, the EEPROM-based EPM7256SQC208-7 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.The EPM7256SQC208-7N devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.

Parametrics

EPM7256SQC208-7N absolute maximum ratings: (1)VCC, Supply voltage: –2.0 to 7.0 V when With respect to ground; (2)VI, DC input voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150℃; (5)TAMB, Ambient temperature Under bias: –65 to 135℃; (6)TJ, Junction temperature Ceramic packages, under bias: 150℃; PQFP and RQFP packages, under bias: 135℃.

Features

EPM7256SQC208-7N features: (1)High-performance, EEPROM-based programmable logic devices; (2)(PLDs) based on second-generation MAXR architecture; (3)5.0V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices, ISP circuitry compatible with IEEE Std. 1532; (4)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (5)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (7)5ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (8)PCI-compliant devices available.